The term Blocking assignment confuses people because the word blocking would seem to suggest time-sequential logic. But in synthesized logic it does not mean this, because everything operates in parallel.
Perhaps a less confusing term would be immediate assignment, which would still differentiate the intermediate results of combinational logic from the inputs to non-transparent memory elements (for example clocked registers), which can have delayed assignment.
From a legalistic standpoint, it all works out very nicely. You can, in fact, consider the to be a blocking (time-sequential) operation even within sequences. However, the distinction between time-sequential and parallel makes absolutely no difference in this case because the block is defined to repeat until the instruction sequence converges on a stable state -- which is exactly what the hardware circuitry will do (if it meets the timing requirements).
The synthesizable subset of Verilog (and especially SystemVerilog) is extremely simple and easy to use -- once you know the necessary idioms. You just have to get past the clever use of terminology associated with the so-called behavioral elements in the language.
answered Jan 10 '15 at 19:49
Если бы возникла проблема, он тут же позвонил бы. Мидж долго молчала. Джабба услышал в трубке вздох - но не мог сказать, вздох ли это облегчения.